Frequently Asked Question

Here are two benchmark cases that can help you estimate the maximum number of buses per standard processing core (SPC). Knowing this is useful both to existing users who already have access to HIL device, and those who are deciding on what device to purchase for their project.

Case 1: No power electronics converters, 10 us time step
Model for HIL604 contains:

• 768 three-phase RL loads
• 960 three-phase RL sections
• 1440 inst. voltage measurement points
• 1440 inst. current measurement points
• No contactors
• No transformers

With this model complexity rough estimation is 120 buses per core. An estimation table for several HIL device models is provided below:

Case 2: With power electronics converters, 10us time step
Model for HIL604 contains:

• No transformers
• 40 contactors
• 768 three-phase RL loads
• 960 three-phase RL sections
• 1440 inst. voltage measurement points
• 1440 inst. current measurement points
• 8 x 3-phase PE converters

Model of this size and complexity would have to be reduced to 20 buses per core. Furthermore, because of number of contactors and PE converters such model could only be supported on HIL604/HIL606. For other devices it would have to be trimmed down due to limitations on the number of contactors and three-phase PE converters (see the table below).

To learn more about how HIL resources of different devices are distributed please check the Device Table in the Firmware Manager or Schematic Settings.

Additionally you will find the Case 1 benchmark model attached. Feel free to experiment wit model complexity vs. hardware utilization by making modifications according to your needs and running compilation afterwards. If the compilation is successful for the selected HIL Device/configuration, this means that your model fits the actual HIL device you have or evaluating for purchase.