Frequently Asked Question

Modeling of Modular Multilevel Converter (MMC) can be demanding of HIL hardware resources but even more so for IO interface requirements. The MMC modeling approach and chosen control method modify these requirements. Moreover, the user application decides if both hardware processing power and IO requirements are to take into account.

If you are primarily interested in real-time SIL (model-based controller implemented in Signal Processing) then there are no IO limitations.

For C-HIL testing with an external controller, the IO number can become a more limiting factor than hardware processing power requirements.

In this FAQ article, maximum simulation capabilities of the Single phase MMC converter connected to the RLC load are presented. The circuit topology is displayed below:

Converter phase leg has two arms, an upper and a lower. Each one is constituted by n number of sub-modules (SMs). The number of voltage levels can be expressed as:

no. of SM/2 + 1

The models for these HIL sizing tests utilize IGBT leg component as the Submodule building block. Therefore, the model is primarily limited by the available number of SPCs and maximum converter weight per SPC. The number of required AOs is not taken into consideration here. Tests are done for the setup containing one HIL device and for the setup containing two HIL devices. Corresponding models are attached.

The table shows HIL sizing results: