Frequently Asked Question

What is the maximum switching frequency supported?
Last Updated 2 years ago

There are several factors to consider when determining the maximum switching frequency for which the HIL simulation provides high-fidelity results. Some of these factors require highly domain-specific knowledge and a deep understanding of the model and control strategy being implemented. Additionally, this value varies for different HIL devices and simulation settings.

The main factors are highlighted below:

  • Simulation time step
  • Converter topology and parametrization
  • Effective PWM resolution
  • HIL device

1. Simulation time step

      Real-time simulation devices run in discrete time with a fixed time step. The simulation time step defines the resolution of the simulation and therefore should be small enough to adequately represent the dynamics of the system, which may include the fast-switching events. Let's assume that N=Tsw/Ts is the ratio between the switching period and the simulation time step, that is, it represents how many times the discrete model of the system is calculated and state variables are updated within the switching period.

      Theoretically, following the Nyquist-Shannon theorem, N>2 is a sufficient condition to uniquely represent a continuous signal of finite bandwidth with a discrete sequence of samples. However, this theorem only applies to a specific class of mathematical functions. In practice, as a rule of thumb, N>10 should be considered to achieve suitable simulation results and, more conservatively, N>100 should provide high fidelity simulation even for the most demanding applications.

      For example, if we consider Ts=200 ns, for N>10 to hold, the maximum switching frequency would be theoretically limited to 500 kHz. Nevertheless, the simulation resolution required depends on the desired model fidelity, which varies according to the application and the responses of interest, as well as with the control and modulation strategies being implemented.

      The minimum simulation time step achievable (and therefore the maximum switching frequency) depends on the HIL device and the complexity of the model.

      The third-generation devices (HIL402, HIL602+, and HIL604) have a minimum simulation time step down to 500 ns, while the fourth-generation devices can go as low as 200 ns. However, the actual minimum simulation time step achievable for a given model is calculated by the compiler (time slot utilization, in the compiler log), taking into account the constraints imposed by the real-time simulation. Modeling optimization techniques such as model partitioning can be employed to reduce the simulation time step, if necessary.   

      2. Converter topology and parametrization

          The compilation process considers a piece-wise linear approach, for which a fixed state space representation is considered within each simulation setup. Therefore, depending on the topology being simulated and the respective parameters (time constants), lower simulation time steps may be required to accurately represent faster dynamic responses. Naturally, the acceptable simulation error for a given application depends on the user requirements and the simulation objectives.

          In addition, some power electronics converter topologies can be more computationally demanding to simulate in real-time with high fidelity, imposing stricter limitations on the maximum switching frequency.

          One example involves resonant converters with passive rectifiers. In this case, the states of naturally commutated devices (diodes) depend on the voltage across them and the current through them. At the same time, the solution for these quantities depends on the state of the device. This imposes significant constraints for real-time simulation; once the time step is discrete and fixed, iterative algorithms are not suitable because computation time is strictly limited.

          To overcome that, converter components are optimized. Nevertheless, the switching frequency limitation can be significantly stricter depending on the topology.

          3. Effective PWM resolution

          Another important limiting factor for determining maximum switching frequency is the effective resolution of the converters’ gate drive signals (GDS), which are usually pulse-width modulated (PWM).

          In the case of software-in-the-loop simulations using the internal modulator, high frequency switch driving signals can be generated from the references (modulating signals) calculated within the model. The internal modulator is implemented on a dedicated hardware unit that operates at the device's clock frequency, which allows for generating high-resolution symmetrical triangular carriers from 100 Hz up to 500 kHz. If a converter does not have an internal modulator, the PWM modulator component can be used. More information can be found in this article.

          When using an external controller to generate the GDS (controller-HIL approach), the digital inputs can be oversampled at the device's clock frequency, and the states compensated to minimize the effects of the sampling error. There are two different algorithms that rely on GDS oversampling to improve simulation results. For more information, please refer to the GDS Oversampling documentation.

          It is important to highlight that the resolution of the internal/PWM modulators as well as the digital input sampling resolution do not rely on the simulation time step, but on the clock frequency of the HIL device.

          For instance, the fourth-generation devices have a digital input sample rate of 280 MSPS, which allows oversampling of gate drive signals (PWM signals) with a period of 3.5 ns. That provides a PWM resolution of 10 bits for converters operating with PWM frequencies around 300 kHz. Meanwhile, the third-generation devices have a digital input sample rate of 160 MSPS, which allows oversampling of gate drive signals (PWM signals) with a period of 6.25 ns. That provides a PWM resolution of 10 bits for converters operating with PWM frequencies around 150 kHz.

          For the sake of comparison, the sampling period of the gate drive signals of an external controller would be equal to the simulation time step if the oversampling is not enabled. In this case, assuming Ts=500 ns (the minimum time step for third-generation devices), the PWM frequency would need to be limited to around 2 kHz in order to achieve a PWM resolution of at least 10 bits. This illustrates how new generation devices and the enhancements on the effective sampling resolution enable high fidelity real-time simulation results for high switching frequency applications.

          For more information, please refer to the IO Timing section of the HIL 4/6 Series Hardware User Guide.

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