Frequently Asked Question

To utilize maximum computational power from the Typhoon HIL emulator, sooner or later you will need to parallelize your model for it to work on multiple FPGA cores. Before starting, it is important to learn some basic modeling principles, especially our system architecture basics.

The way parallelization is done in our environment is by using electrical circuit partitioning. In order to do that you can use different circuit partitioning components, of which the most important is the IT (Ideal Transformer) core coupling. This type of component is best suited when creating power electronics models. For power systems and microgrid applications however, TLM (Transmission Line Model) couplings are more suited. This component can be used on its own or embedded inside other components, such as in the RL section.

For achieving simulation stability and accuracy, it is crucial to perform correct coupling placement and parametrization. In some cases, adding a coupling element in a circuit may create topological conflicts. In order to avoid them, you will need to include snubber circuits.

You are also able to map portions of different signal processing parts of your model onto different CPU cores. This is done by using CPU Markers. Data transfer between components that operate on different CPU cores on the same device is managed by the CPU Transition component.

For complex models which require even more computational power than what a single HIL device can provide, you can map different parts of the model onto different HIL devices, using Device Markers. Of course, this can only be done in multiple HIL configurations. Partitioning the model across different devices is done using IT or TLM Device Couplings.

Some of the previously mentioned topics are covered in our Video Knowledgebase:

Electrical circuit partitioning

If you want to learn more about previous concepts we highly recommend you to enroll in our HIL Specialist 2.0 Specialization program course on our HIL Academy platform.