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TRANSCRIPT
Hello!
In previous lessons we discussed about electricalcircuit partitioning.
We explored how to deal with core couplings,snubbers, and how electrical circuit components
impacts to your model.
In this lesson we will focus more on the signalprocessing part of the circuit.
As explained in the previous module 3.2.
Problems & solutions of real-time modeling,sometimes it is needed to execute the signal
processing part of the circuit at an executionrate that is lower than is typically used
in most applications.
If the CPU cannot manage to run code in thegiven time slot, HIL SCADA will warn us with
the computing interval overrun or CIO flag.
The 4th generation HIL404 and HIL606 can grantyou even faster execution rates than the previous
generation devices.
They also support signal processing partitioningbetween cores, which allows parallel computation
of signal processing code.
Signal processing partitioning also makesit possible to exchange data between multiple
cores.
In order to manage Signal processing partitioning,there are two components: CPU marker and CPU
transition.
CPU marker is used to map a portion of thesignal processing model to the specified CPU
core.
They are only available on devices with multipleUser CPU cores.
If we double click on the mask, you can seea marker's identification label that specifies
in which CPU core the marked part of the circuitwill be executed.
CPU Transition manages data transfer betweencomponents that operate on different CPU cores
of the same device.
In order for two Signal Processing circuitsthat run on different User CPUs of the same
device to exchange data, they should be connectedusing the CPU Transition component.
Including CPU Transition components can introducea delay of one execution rate.
You can find more details about this componentin the Materials tab.
When it comes to signal processing partitioningbetween cores, there are two modes of operation.
By clicking on Model settings then signalprocessing settings and the CPU mapping option,
you can see the default and execution rate-basedoperation modes.
By enabling the default mode of operation,CPU marker components apply to the connected
Signal Processing component group.
Component groups with no CPU markers are mappedto CPU core 0.
CPU Transition components are used as separatorsfor CPU partitioning.
The other option is the execution rate-basedmode of operation, which allows model mapping
on multiple CPU cores without the need touse CPU transition and CPU marker components.
CPU partitioning is done based on the executionrates present in the model.
In this way, rate transition components, whichare explained in more detail in the documentation
link in the Materials tab, can also serveas separators for CPU partitioning.
When CPU markers are used, they apply to allcomponents that have the same execution rate.
When CPU markers are not used, the compilerautomatically maps execution rates to the
available CPU cores.
Now let s see an example of when signal processingpartitioning components should be used and
how.
For this example s purpose, a HIL 404 is used.
As you can see this example is very simpleand contains only a signal processing part.
Let s imagine we are performing harmonic analysisfor different harmonics.
The first harmonic analyzer is used for the1st, 3rd, 5th, and 7th harmonic, and the second
one is used for the 9th, 11th, 13th, and 15th.
The signal processing execution rate is 6microseconds.
Now let s compile this model and run the simulation.
As you can see, the compilation finishes successfully,but when we run our simulation, the CIO flag
pops up, warning us that the signal processingcode can t be executed in the given time slot
of 6 microseconds.
If we click on the CIO flag, we can see thatthe User CPU is 100% used.
The troubleshooting process implies signalprocessing partitioning can be a solution.
Now let s go back to the model and dividethis circuit in two cores.
Let s put one harmonic analyzer in one coreand the other one in another core.
Let s choose CPU transition and put the executionrate to Ts.
Lastly, let s mark which part will be executedon which core.
If we compile and run the model again, asis expected, we don t have the CIO flag raised.
If we click on that window, we can see thatUser CPU utilization is equally divided between
the cores.
Here it is important to notice that CPU mappingin the Signal processing settings is set to
Default.
Now let s see how we can use execution rate-basedCPU mapping.
Let s first use a transition rate insteadof CPU transition.
The execution rate of the circuit after thatcomponent will be two times larger than the
execution rate before the rate transition.
If we compile the model with default CPU mapping,we can see in the message console that this
model is in one CPU core as is expected.
Now when we run the simulation, we get a CIOerror.
Let s change the CPU mapping option to Executionrate based and re-run the model.
In the message console, we can see that themodel is divided in two CPU cores.
If we run the simulation, now we can see thatthe computing interval overrun issue is solved.
Signal processing core partitioning is particularlyuseful for microgrid systems which contain
signal processing based (generic) components.
Those components will be explained in moredetail in Module 5, HIL for Microgrids.
With this lesson, we ve now covered all theimportant aspects of core partitioning.
In the next lesson, device partitioning willbe highlighted in more detail.
So, see you there.
Thank you for watching!
