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In the previous lesson we briefly touchedon the topic of compiler warnings as well
as core coupling orientation.
In this lesson we will discuss topologicalconflicts, which are important to fully understand
the compiler warnings resulting from electricalmodel degenerations, as well as partitioning
problems associated with placement, orientation,and parametrization of ideal transformer core couplings.
So, what are Topological Conflicts?
Topological conflicts are a set of modelingproblems that arise due to a specific combination
of elements within the ideal electrical circuit,which can cause unexpected or incorrect simulation
Let’s start with an overview of all thetopological conflicts that could occur.
There are two main types of topological conflicts– state degenerations and source degenerations.
Let’s dive into state degenerations.
State degenerations are topological conflictsthat occur when either the voltage source
is connected in parallel with capacitor orthe current source is connected in series
In the first case, the capacitor gets degenerated,meaning that the circuit behaves in exactly
the same way as if there was no capacitorconnected at all.
The same occurs to the inductor in the secondcase.
Let’s see what will happen if some of thesedegenerations occur in our model.
Now, let’s add capacitor in parallel tothe voltage source.
[silence for 30 second] When we compile thismodel, we receive a warning about a bad voltage
loop which is detected and that capacitoris degenerated.
Basically, this warning is informing us thatthe capacitor has no impact on the circuit.
This error should be familiar if you rememberthe previous lesson, since it was discussed
there as well.
However, this warning is slightly differentthen the classical “bad voltage loop”
warning, and should be dealt with differently.
The reason why this is different is becauseregardless of the switch permutations, degeneration
will still stay, even though the error messageonly mentions one particular switch arrangement
where this occurs.
Therefore, it is important that you can recognizethese degenerations and know why the warning
You might already have sense about how tofix this issue – simply altering the circuit
by adding a snubber would fix this issue.
Snubbers are elements that are used to increasethe stability to the simulation.
They are also an important part of model partitioning,and therefore we will look into them in much
more detail in the next lessons that dealwith model partitioning.
In this case, snubber elements should be addedin series to the voltage source or in parallel
to the current source.
Let’s now talk about the next topologicalconflict type – source degenerations.
There are two types of source degenerations,
direct degeneration of independent sourcesand of independent sources with zero sources.
We’ll first explain the direct degenerationof independent sources.
Degeneration of independent sources occurswhen there are multiple voltage sources in
parallel or multiple current sources in series.
These degenerations won’t cause an errorduring compilation but instead will stop the
compilation process completely.
Let’s see this in our example.
Let’s add a voltage source in parallel withthe already existing voltage source.
When we compile, we receive an error thatstops the compilation completely and therefore
requires us to either remove the surplus ofsources, or to include passive elements in between.
Let’s go to the second source degeneration.
The second source degeneration is the directdegeneration of independent sources with zero source.
In this case, zero sources are open and closedswitches.
These topological conflicts occur when thereis a closed switch in parallel with a voltage
source or when an open switch is in serieswith current sources.
When this happens, the switches become degenerated– meaning that in the case where we have
a switch and voltage source in parallel, theswitch will always be open, no matter what
control signal it receives.
Additionally, any switch in series of a currentsource will always be closed, no matter the
This means that having switches in parallelwith voltage sources and switches in series
of current sources has no effect on the circuitat all.
Let’s see how this impacts the compilationprocess.
Let’s add a switch in parallel to the voltagesource in the model.
[silence for 25 second] Now, when we compilethis model, we receive an error which warns
us that the switch we added is degenerated.
We have once again received a warning thatpoints us to the specific converter arrangement,
however this type of degeneration is independentof the converter permutation so you should
fix the topology in general, not just forthe particular case of this one switch permutation
that the compiler warned us about.
The compiler will not stop us from loadingthis model, however: it will simply ignore
these switches during simulation.
These issues can be fixed by adding snubbers,or more precisely by adding a snubber in series
to the voltage source or in parallel to thecurrent source.
The topic of snubbers will be expanded inlesson 3.3, Model Partitioning, where we address
the problem of snubber parametrization insidethe ideal transformer core couplings.
In this lesson, we have covered every typeof topological conflict.
If you want to learn more about them, pleaserefer to the documentation link in the materials section.
Thank you for your attention.