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**TRANSCRIPT**

Hello! In this video we will explain the basics of model partitioning in Typhoon HIL software.

You will have a chance to learn about the motivation behind it,

different types of model partitioning, and the practical benefits that you can gain from it.

First, let’s recap the basics of Typhoon HIL’s modeling approach.

Testing complex power electronics and microgrid plants with high fidelity

can be challenging for a real time platform. Typhoon HIL’s solution accomplishes this by

modeling every switch state permutation with a linear and time-invariant circuit model.

In this approach, every circuit mode is represented as a state space model.

As we want to reduce computation during runtime, all state space matrices are calculated during

the model compilation process and stored in the FPGA solver memory.

However, this approach comes with its own price. The number of modes per circuit is

equal to 2 to the power of n, where n is the total number of switching elements.

As we can see the number of modes grows exponentially with the number of switches

in the circuit, which puts a very high strain on circuit solver memory resources.

For the example, let’s take a look at a two level three-phase back to back converter. This converter

topology in the general case has n switches in one converter and m switches in the other converter.

Here we are considering IGBT-diode pairs as single switches. Besides IGBTs and diodes, ideal

contactors are also considered as switches. In our example we have six switches in both converters,

which makes 12 switching elements in total. If we do our calculation, 2 to the power of 12, we

are getting more than 4000 state space matrices, which needs to be stored in our device memory.

Not to mention that every additional switch would double this number. It is clear that

with this exponential memory growth, we cannot scale above a certain level of complexity.

The solution for overcoming this obstacle is to divide a complex circuit into multiple

subcircuits. This way we can keep the number of switches per model at a manageable level. In

this approach every subcircuit is represented and calculated independently with its own mode set.

In order to make subcircuits behave as the original circuit, they need to share

information. This is done through variable exchange; we will talk more about this later.

Now, going back to our buck to buck example, we can see that if we split the model so that one

converter is placed in one subcircuit, and the other one is placed in the other subcircuit, we

can achieve a total of 64 modes for each circuit. In this way the total number of modes goes from

the original 4096 to only 128, effectively linearizing our exponential memory growth problem.

As a result of this we have significantly reduced memory

requirements and enabled the FPGA solver to calculate the model in parallel.

The important aspect of Typhoon simulation is the ability to scale the model size

while maintaining simulation fidelity. On this slide you can see an example of a typical power

electronics application running on one core with a simulation step of half a microsecond. Adding more

converters will increase the computational load, but not noticeably. More importantly

due to a low latency interconnection between SPCs, it is possible to maintain low simulation step

even in case of occupying all cores with complex converter topologies.

There are two basic types of model partitioning: electrical circuit and signal processing.

Electrical partitioning can be achieved by dividing the model in multiple FPGA cores,

or with multi-HIL setups, dividing the model between several HIL devices working in parallel.

A similar concept applies for the signal processing part of the model,

which can be allocated to multiple CPU cores or across multiple HIL devices working in parallel.

In this way, signal processing computations will be shared among multiple CPUs, which allows for

a lower execution rate. These concepts will be shown in more detail in the next lessons.

Let’s now sum-up all the benefits that you can get from model partitioning.

The first and the most obvious advantage is that you can simulate power electronics

models with a large number of switches and contactors. The same principle applies for

complex microgrid and power system models with lots of nodes and Distributed Energy Resources.

The next really important point is that since the simulation is divided into multiple cores, you

will be able to utilize parallel computing which allows you to preserve a low simulation step.

As you can see in the table on the right side, there are certain resources that are dedicated

for every standard processing core. This means that if you divide your circuit across SPCs,

each partitioned segment of your model will have these resources available. Lastly, a nice

advantage of partitioning is that the compilation process will typically be notably shortened.

This video has covered basics of model partitioning. In the next one, we will focus

more on electrical circuit partitioning.

Thank you for your attention.